NCERT Solutions for Class 12 Science Physics Chapter 6, titled “Semiconductor Electronics: Materials, Devices And Simple Circuits,” offer comprehensive explanations with step-by-step guidance. These solutions are widely favored by Class 12 Science students for Physics, as they prove invaluable for completing assignments and preparing for exams. All the questions and answers from this chapter in the NCERT Book are provided here for free, aiding students in their understanding of Semiconductor Electronics: Materials, Devices And Simple Circuits.

**Page No 509:**

**Question 14.1:**

In an n-type silicon, which of the following statement is true:

**(a)** Electrons are majority carriers and trivalent atoms are the dopants.

**(b)** Electrons are minority carriers and pentavalent atoms are the dopants.

**(c)** Holes are minority carriers and pentavalent atoms are the dopants.

**(d)** Holes are majority carriers and trivalent atoms are the dopants.

**ANSWER:**

The correct statement is **(c)**.

In an n-type silicon, the electrons are the majority carriers, while the holes are the minority carriers. An n-type semiconductor is obtained when pentavalent atoms, such as phosphorus, are doped in silicon atoms.

**Page No 509:**

**Question 14.2:**

Which of the statements given in Exercise 14.1 is true for p-type semiconductors.

**ANSWER:**

The correct statement is **(d).**

In a p-type semiconductor, the holes are the majority carriers, while the electrons are the minority carriers. A p-type semiconductor is obtained when trivalent atoms, such as aluminium, are doped in silicon atoms.

**Page No 509:**

**Question 14.3:**

Carbon, silicon and germanium have four valence electrons each. These are characterised by valence and conduction bands separated by energy band gap respectively equal to (*E*_{g})_{C}, (*E*_{g})_{Si }and (*E*_{g})_{Ge}. Which of the following statements is true?

**(a) **(*E*_{g})_{Si }< (*E*_{g})_{Ge} < (*E*_{g})_{C}

**(b) **(*E*_{g})_{C} < (*E*_{g})_{Ge} > (*E*_{g})_{Si}

**(c) **(*E*_{g})_{C} > (*E*_{g})_{Si} > (*E*_{g})_{Ge}

**(d) **(*E*_{g})_{C} = (*E*_{g})_{Si }= (*E*_{g})_{Ge}

**ANSWER:**

The correct statement is **(c)**.

Of the three given elements, the energy band gap of carbon is the maximum and that of germanium is the least.

The energy band gap of these elements are related as: (*E*_{g})_{C} > (*E*_{g})_{Si} > (*E*_{g})_{Ge}

**Page No 509:**

**Question 14.4:**

In an unbiased p-n junction, holes diffuse from the p-region to n-region because

**(a) **free electrons in the n-region attract them.

**(b) **they move across the junction by the potential difference.

**(c) **hole concentration in p-region is more as compared to n-region.

**(d) **All the above.

**ANSWER:**

The correct statement is **(c)**.

The diffusion of charge carriers across a junction takes place from the region of higher concentration to the region of lower concentration. In this case, the p-region has greater concentration of holes than the n-region. Hence, in an unbiased p-n junction, holes diffuse from the p-region to the n-region.

**Page No 510:**

**Question 14.5:**

When a forward bias is applied to a p-n junction, it

**(a) **raises the potential barrier.

**(b) **reduces the majority carrier current to zero.

**(c) **lowers the potential barrier.

**(d) **None of the above.

**ANSWER:**

The correct statement is **(c)**.

When a forward bias is applied to a p-n junction, it lowers the value of potential barrier. In the case of a forward bias, the potential barrier opposes the applied voltage. Hence, the potential barrier across the junction gets reduced.

**Page No 510:**

**Question 14.6:**

For transistor action, which of the following statements are correct:

**(a) **Base, emitter and collector regions should have similar size and doping concentrations.

**(b) **The base region must be very thin and lightly doped.

**(c) **The emitter junction is forward biased and collector junction is reverse biased.

**(d) **Both the emitter junction as well as the collector junction are forward biased.

**ANSWER:**

The correct statement is **(b)**, **(c)**.

For a transistor action, the junction must be lightly doped so that the base region is very thin. Also, the emitter junction must be forward-biased and collector junction should be reverse-biased.

**Page No 510:**

**Question 14.7:**

For a transistor amplifier, the voltage gain

**(a) **remains constant for all frequencies.

**(b) **is high at high and low frequencies and constant in the middle frequency range.

**(c) **is low at high and low frequencies and constant at mid frequencies.

**(d) **None of the above.

**ANSWER:**

The correct statement is **(c)**.

The voltage gain of a transistor amplifier is constant at mid frequency range only. It is low at high and low frequencies.

**Page No 510:**

**Question 14.8:**

In half-wave rectification, what is the output frequency if the input frequency is 50 Hz. What is the output frequency of a full-wave rectifier for the same input frequency.

**ANSWER:**

Input frequency = 50 Hz

For a half-wave rectifier, the output frequency is equal to the input frequency.

∴Output frequency = 50 Hz

For a full-wave rectifier, the output frequency is twice the input frequency.

∴Output frequency = 2 × 50 = 100 Hz

**Page No 510:**

**Question 14.9:**

For a CE-transistor amplifier, the audio signal voltage across the collected resistance of 2 kΩ is 2 V. Suppose the current amplification factor of the transistor is 100, find the input signal voltage and base current, if the base resistance is 1 kΩ.

**ANSWER:**

Collector resistance, *R*_{C} = 2 kΩ = 2000 Ω

Audio signal voltage across the collector resistance, *V* = 2 V

Current amplification factor of the transistor, *β* = 100

Base resistance, *R*_{B} = 1 kΩ = 1000 Ω

Input signal voltage = *V*_{i}

Base current = *I*_{B}

We have the amplification relation as:

Voltage amplification

Therefore, the input signal voltage of the amplifier is 0.01 V.

Base resistance is given by the relation:

Therefore, the base current of the amplifier is 10 μA.

**Page No 510:**

**Question 14.13:**

In an intrinsic semiconductor the energy gap *E*_{g}is 1.2 eV. Its hole mobility is much smaller than electron mobility and independent of temperature. What is the ratio between conductivity at 600K and that at 300K? Assume that the temperature dependence of intrinsic carrier concentration *n*_{i}is given by

where *n*_{0 }is a constant.

**ANSWER:**

Energy gap of the given intrinsic semiconductor, *E*_{g} = 1.2 eV

The temperature dependence of the intrinsic carrier-concentration is written as:

Where,

*k*_{B} = Boltzmann constant = 8.62 × 10^{−5} eV/K

T = Temperature

*n*_{0} = Constant

Initial temperature, *T*_{1} = 300 K

The intrinsic carrier-concentration at this temperature can be written as:

… (1)

Final temperature, *T*_{2} = 600 K

The intrinsic carrier-concentration at this temperature can be written as:

… (2)

The ratio between the conductivities at 600 K and at 300 K is equal to the ratio between the respective intrinsic carrier-concentrations at these temperatures.

Therefore, the ratio between the conductivities is 1.09 × 10^{5}.

**Page No 511:**

**Question 14.14:**

In a p-n junction diode, the current I can be expressed as

where *I*_{0} is called the reverse saturation current, *V *is the voltage across the diode and is positive for forward bias and negative for reverse bias, and *I *is the current through the diode, *k*_{B}is the Boltzmann constant (8.6×10^{−5} eV/K) and T is the absolute temperature. If for a given diode *I*_{0} = 5 × 10^{−12 }A and T = 300 K, then

**(a) **What will be the forward current at a forward voltage of 0.6 V?

**(b) **What will be the increase in the current if the voltage across the diode is increased to 0.7 V?

**(c) **What is the dynamic resistance?

**(d) **What will be the current if reverse bias voltage changes from 1 V to 2 V?

**ANSWER:**

In a p-n junction diode, the expression for current is given as:

Where,

*I*_{0} = Reverse saturation current = 5 × 10^{−12} A

*T* = Absolute temperature = 300 K

*k*_{B} = Boltzmann constant = 8.6 × 10^{−5} eV/K = 1.376 × 10^{−23} J K^{−1}

V = Voltage across the diode

**(a)** Forward voltage, *V* = 0.6 V

∴Current, *I*

Therefore, the forward current is about 0.0256 A.

**(b)** For forward voltage, *V*^{’} = 0.7 V, we can write:

Hence, the increase in current, Δ*I *= *I*^{‘} − *I*

= 1.257 − 0.0256 = 1.23 A

**(c)** Dynamic resistance

**(d)** If the reverse bias voltage changes from 1 V to 2 V, then the current (*I*) will almost remain equal to *I*_{0} in both cases. Therefore, the dynamic resistance in the reverse bias will be infinite.

**Page No 511:**

**Question 14.15:**

You are given the two circuits as shown in Fig. 14.44. Show that circuit (a) acts as OR gate while the circuit (b) acts as AND gate.

**ANSWER:**

**(a) ***A* and *B* are the inputs and *Y* is the output of the given circuit. The left half of the given figure acts as the NOR Gate, while the right half acts as the NOT Gate. This is shown in the following figure.

Hence, the output of the NOR Gate =

This will be the input for the NOT Gate. Its output will be = *A* + *B*

∴*Y* = *A* + *B*

Hence, this circuit functions as an OR Gate.

**(b) ***A* and *B* are the inputs and *Y* is the output of the given circuit. It can be observed from the following figure that the inputs of the right half NOR Gate are the outputs of the two NOT Gates.

Hence, the output of the given circuit can be written as:

Hence, this circuit functions as an AND Gate.

**Page No 511:**

**Question 14.16:**

Write the truth table for a NAND gate connected as given in Fig. 14.45.

Hence identify the exact logic operation carried out by this circuit.

**ANSWER:**

*A* acts as the two inputs of the NAND gate and *Y* is the output, as shown in the following figure.

Hence, the output can be written as:

The truth table for equation (*i*) can be drawn as:

A | Y |

0 | 1 |

1 | 0 |

This circuit functions as a NOT gate. The symbol for this logic circuit is shown as:

**Page No 511:**

**Question 14.17:**

You are given two circuits as shown in Fig. 14.46, which consist of NAND gates. Identify the logic operation carried out by the two circuits.

**ANSWER:**

In both the given circuits, *A* and *B* are the inputs and *Y* is the output.

**(a)** The output of the left NAND gate will be, as shown in the following figure.

Hence, the output of the combination of the two NAND gates is given as:

Hence, this circuit functions as an AND gate.

**(b)** is the output of the upper left of the NAND gate and is the output of the lower half of the NAND gate, as shown in the following figure.

Hence, the output of the combination of the NAND gates will be given as:

Hence, this circuit functions as an OR gate.

**Page No 511:**

**Question 14.18:**

Write the truth table for circuit given in Fig. 14.47 below consisting of NOR gates and identify the logic operation (OR, AND, NOT) which this circuit is performing.

(Hint: A = 0, B = 1 then A and B inputs of second NOR gate will be 0 and hence Y=1. Similarly work out the values of Y for other combinations of A and B. Compare with the truth table of OR, AND, NOT gates and find the correct one.)

**ANSWER:**

*A* and *B* are the inputs of the given circuit. The output of the first NOR gate is. It can be observed from the following figure that the inputs of the second NOR gate become the out put of the first one.

Hence, the output of the combination is given as:

The truth table for this operation is given as:

A | B | Y (=A + B) |

0 | 0 | 0 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 1 |

This is the truth table of an OR gate. Hence, this circuit functions as an OR gate.

**Page No 512:**

**Question 14.19:**

Write the truth table for the circuits given in Fig. 14.48 consisting of NOR gates only. Identify the logic operations (OR, AND, NOT) performed by the two circuits.

**ANSWER:**

**(a) ***A* acts as the two inputs of the NOR gate and *Y* is the output, as shown in the following figure. Hence, the output of the circuit is.

The truth table for the same is given as:

A | Y |

0 | 1 |

1 | 0 |

This is the truth table of a NOT gate. Hence, this circuit functions as a NOT gate.

**(b) ***A* and *B* are the inputs and *Y* is the output of the given circuit. By using the result obtained in solution **(a)**, we can infer that the outputs of the first two NOR gates areas shown in the following figure.

are the inputs for the last NOR gate. Hence, the output for the circuit can be written as:

The truth table for the same can be written as:

A | B | Y (=A⋅B) |

0 | 0 | 0 |

0 | 1 | 0 |

1 | 0 | 0 |

1 | 1 | 1 |

This is the truth table of an AND gate. Hence, this circuit functions as an AND gate.